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Moved!
2007-10-13 07:12:00 This blog has moved to it’s own add-on domain, http://www.vlsihomepage.com. Please do bookmark it and visit often for updates. As usual, any feedback/suggestions to improve the blog are welcome. Share This
Cyclic Redundancy Check (CRC)
2007-10-12 08:12:00 CRC-16 and CRC-32 algorithms are widely used in diverse communication protocols for robustness. The basic idea behind CRC is that the transmitter computes a string of bits called frame check sequence (or checksum) for each frame based on it’s contents and appends it to the end of the message before sending it ... More About: Check
Effective Executive by Peter Drucker
2007-10-04 19:22:00 Effectiveness must be learned as an executive is paid for being effective asserts Drucker, the management guru. Effectiveness is the ability to get the right things done and is a habit, a complex of practices that have to be acquired. Outlined below are the steps that could make you more effective according to his ... More About: Career , Executive , Effective , Peter , Peter Drucker
How to have a successful career
2007-10-04 19:19:00 Imagine a workplace that you look forward to go to everyday - you hold the position you coveted for, enjoy the work and the benefits that come along with it, you are held in high esteem by your colleagues, have a say in the direction the organization is heading and pride on being ... More About: Career
Serial to Parallel and Parallel to Serial conversion
2007-10-03 18:11:00 Serial to Parallel conversion is common in designs where the clock runs at slower frequency than the incoming serial stream. To maintain the throughput, the serial data is converted to parallel data. Similarly, high speed parallel data can be converted to serial stream before output from a chip - as ... More About: Conversion , Serial
RTL coding guidelines - Doing it right the first time!
2007-09-27 19:39:00 Document in detail interface timing and signal descriptions, clock and reset strategy, modular view of the design and FSMs prior to RTL coding. Have a comment “header” for each module with functionality description, version and a log of past changes. This can be managed using a revision control system like CVS. Do not include more than ... More About: Time , Coding , Guidelines , First Time , Odin
On chip variation and CRPR
2007-09-27 17:45:00 Static timing analysis in a chip is largely dependent on Process, Temperature and Voltage variations (PVT), the cell delays and interconnect delays vary largely with these factors. Hence it is necessary to run timing analysis in both worst and best case operating conditions and ensure we meet setup/hold requirements for the chip. For worst case corners, ... More About: Chip
Logic BIST Design
2007-09-24 19:05:00 Need for Logi c Built-in Self Test (BIST) Traditional scan requires large number of vectors to sensitize the design, runs at a maximum frequency of 50 MHz and is limited by number of channels supported by the tester. All these add to tester time that varies from 25 to 50 cents per second. Many designs integrate ... More About: Design
DFT - Traditional Scan
2007-09-22 19:48:00 Traditional scan based designs employ either Muxed-scan technique or Level Sensitive Scan Design (LSSD) techniques to achieve test coverage. In scan based designs, the registers are hooked up to form serial shift register chains - this aids in capturing all the combinational logic faults between two pipelined registers. There is a shift phase during which the ... More About: Traditional
Design for Testability
2007-09-22 17:07:00 Overview Design for Testa bility (DFT) is one of the critical requirements in a design - additional test logic is added to detect any manufacturing defects such as opens/shorts on a silicon die. A chip or a die can be tested at various levels ( at wafer level, package level, board level, system level or ... More About: Stability |
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